OSCPU/chisel-playground

Generator Bootcamp Material: Learn Chisel the Right Way

For contributions of Chisel IP to the chisel community.

Digital Design with Chisel

Chisel: A Modern Hardware Design Language

A RISC-V Core (RV32I) written in Chisel HDL

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

Rocket Chip Generator

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more