freechipsproject/chisel-bootcamp

Digital Design with Chisel

Chisel: A Modern Hardware Design Language

Learning FPGA, yosys, nextpnr, and RISC-V

Scala based HDL

Rocket Chip Generator

Build your hardware, easily!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

Haskell to VHDL/Verilog/SystemVerilog compiler