fpgadeveloper/fpga-drive-aximm-pcie

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Small footprint and configurable PCIe core

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Build Customized FPGA Implementations for Vivado

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to Gbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: |1| openRTL |2| openBFM with unique SIM and WAVE capabilities, way better than vendor's |3| openSW stack |4| one-of-a-kind open backplane.

A collection of Master XDC files for Digilent FPGA and Zynq boards.

HDL libraries and projects