chili-chips-ba/openPCIE

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

Small footprint and configurable PCIe core

ElemRV - End-to-end Open-Source RISC-V Microcontroller

Linux on LiteX-VexRiscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Isle FPGA Computer

PCILeech firmware generator tool

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

Example designs for FPGA Drive FMC