taichi-ishitani/tvip-axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

The UVM written in Python

Bus bridges and other odds and ends

BaseJump STL: A Standard Template Library for SystemVerilog

Functional verification project for the CORE-V family of RISC-V cores.

cocotb: Python-based chip (RTL) verification