Weiyet/MakerCode_RTLChallenge

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

Digital HDL Design Full-stack Agents

AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.

An open-source benchmark for generating design RTL with natural language

Verilog HDL files

A curated list of awesome resources for HDL design and verification

Design circuit boards with code! ✨ Get software-like design reuse 🚀, validation, version control and collaboration in hardware; starting with electronics ⚡️

AI agent skill for creating, editing and simulating real Proteus circuit projects. It would save lots of EE students

BaseJump STL: A Standard Template Library for SystemVerilog