VHDL-LS/rust_hdl

VHDL 2008/93/87 simulator

All in one vscode plugin for HDL development

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

SystemVerilog language server

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

VHDL compiler and simulator

cocotb: Python-based chip (RTL) verification

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

SystemVerilog compiler and language services