riscv-software-src/riscv-perf-model

Open-source high-performance RISC-V processor

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

RSD: RISC-V Out-of-Order Superscalar Processor

SonicBOOM: The Berkeley Out-of-Order Machine

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

RISC-V CPU simulator for education purposes

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

A graphical processor simulator and assembly editor for the RISC-V ISA