riscv-boom/riscv-boom

RSD: RISC-V Out-of-Order Superscalar Processor

Open-source high-performance RISC-V processor

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Rocket Chip Generator

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

PicoRV32 - A Size-Optimized RISC-V CPU