pulp-platform/ara

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

RISC-V Debug Support for our PULP RISC-V Cores

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Open-source high-performance RISC-V processor

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Like VexRiscv, but, Harder, Better, Faster, Stronger