veripool/verilog-mode

Verilog/SystemVerilog support for VS Code

All in one vscode plugin for HDL development

A SystemVerilog language server based on the Slang library.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

SystemVerilog language server

Style guide enforcement for VHDL

Icarus Verilog