Footer

Your go-to destination for discovering trending open-source projects and uncovering the insights that matter

Legal

  • Terms and conditions
  • Privacy policy

More

  • Pricing
  • Advertise
  • onedump
  • gosnakego
  • Contact us

Social

  • X (Twitter)
  • GitHub
Trendshift owl
What they build speaks louder than words
© 2026 Trendshift, created by Julian Li with ❤️
SignalAdvertise
Trendshift
SignalAdvertise
Sign in
Trendshift owl

Discover trends that matter

DailyWeeklyMonthlyYearly
Live mentionsTopics
RepositoriesDevelopers
InsightsStats

ClawBench
ClawBench
Bifrost
Bifrost
Busbar
Busbar

CESNET/ndk-fpga

Network Development Kit (NDK) for FPGA cards with example application

Visit GitHub
VHDL
99
17
17 contributors
BSD 3-Clause "New" or "Revised" License
website
AchievementsView all →
FeaturedAdvertise to 180K+ monthly visitors
ClawBench

a benchmark for personal agents

Bifrost

Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

Busbar

Control what AI can do before it acts

Momentum

How fast CESNET/ndk-fpga is gaining stars, and where it lands on Trendshift and GitHub Trending

Activity and trending

Stars, forks and merged pull requests each day or month, lined up with the repository's rank on Trendshift Trending

Sep 20 – Oct 22, 2026

Stars +3 in 33 days

01
1

Forks +0 in 33 days

01

Merged PRs 0 in 33 days

01

Trendshift Trendingwhere the repository ranked each day it made the top 25

Top 25 in VHDL

62106
Sep 20Sep 25Sep 30Oct 5Oct 10Oct 15Oct 20
The left and right arrow keys step from day to day; Home and End go to the first and the last

Stars, forks, merged pull requests and Trendshift Trending rank, by day
DayStars gainedForks gainedMerged PRsVHDL
Sun, Sep 20, 2026+1+00#6
Mon, Sep 21, 2026+0+00Not trending
Tue, Sep 22, 2026+1+00#2
Wed, Sep 23, 2026+0+00Not trending
Thu, Sep 24, 2026+0+00Not trending
Fri, Sep 25, 2026+0+00Not trending
Sat, Sep 26, 2026+0+00Not trending
Sun, Sep 27, 2026+0+00Not trending
Mon, Sep 28, 2026+0+00Not trending
Tue, Sep 29, 2026+0+00Not trending
Wed, Sep 30, 2026+0+00Not trending
Thu, Oct 1, 2026+0+00Not trending
Fri, Oct 2, 2026+0+00Not trending
Sat, Oct 3, 2026+0+00Not trending
Sun, Oct 4, 2026+0+00Not trending
Mon, Oct 5, 2026+0+00Not trending
Tue, Oct 6, 2026+0+00Not trending
Wed, Oct 7, 2026+0+00#10
Thu, Oct 8, 2026+1+00#6
Fri, Oct 9, 2026+0+00Not trending
Sat, Oct 10, 2026+0+00Not trending
Sun, Oct 11, 2026+0+00Not trending
Mon, Oct 12, 2026+0+00Not trending
Tue, Oct 13, 2026+0+00Not trending
Wed, Oct 14, 2026+0+00Not trending
Thu, Oct 15, 2026+0+00Not trending
Fri, Oct 16, 2026+0+00Not trending
Sat, Oct 17, 2026+0+00Not trending
Sun, Oct 18, 2026+0+00Not trending
Mon, Oct 19, 2026+0+00Not trending
Tue, Oct 20, 2026+0+00Not trending
Wed, Oct 21, 2026+0+00Not trending
Thu, Oct 22, 2026+0+00Not trending
Total+3+00
  • 1#1 on the list
  • 7Rank that day
  • Not trending
  • Achievements

    Trendshift snapshots GitHub's daily Trending list and runs its own trending list

    Trendshift Trending

    CESNET/ndk-fpga has trended on Trendshift's daily and weekly list

    Daily

    First achieved on 22nd, Sep 2026 for VHDL

    #2 VHDL Repository Of The Day

    Weekly

    First achieved in Week 33, 2026 for VHDL

    #8 VHDL Repository Of The Week

    First achieved on 22nd, Sep 2026 for VHDL

    #2 VHDL Repository Of The Day

    First achieved in Week 33, 2026 for VHDL

    #8 VHDL Repository Of The Week

    You might also like

    Repositories close to CESNET/ndk-fpga
    FeaturedAdvertise to 180K+ monthly visitors
    ClawBench

    a benchmark for personal agents

    Busbar

    Control what AI can do before it acts

    Bifrost

    Enterprise AI Gateway Built For Scale: Route, Govern, and Secure All Your AI Traffic

    open-rdma/open-rdma

    Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other things.

    38454

    fpganinja/taxi

    SystemVerilog

    AXI, AXI stream, Ethernet, and PCIe components in System Verilog

    984151

    enjoy-digital/liteeth

    Python

    Small footprint and configurable Ethernet core

    309111

    aws/aws-fpga

    SystemVerilog

    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

    1.7k528

    fpgadeveloper/ethernet-fmc-axi-eth

    Tcl

    Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

    7636

    fpgadeveloper/fpga-drive-aximm-pcie

    Tcl

    Example designs for FPGA Drive FMC

    305114

    Gabriele-bot/100G-verilog-RoCEv2-lite

    Verilog

    TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

    7832

    tow3rs/catapult-v3-smartnic-re

    VHDL

    Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

    21740

    usnistgov/ndn-dpdk

    Go

    NDN-DPDK: High-Speed Named Data Networking Forwarder

    15427