Gabriele-bot/100G-verilog-RoCEv2-lite

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Network Development Kit (NDK) for FPGA cards with example application

Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other things.

Small footprint and configurable Ethernet core

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, M.2 and Edge cards for GateMate. Project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI...

Example designs for FPGA Drive FMC

CAN FD IP Core in VHDL