PrincetonUniversity/openpiton

Tile based architecture designed for computing efficiency, scalability and generality

A Linux-capable RISC-V multicore for and by the world

ET Accelerator Firmware and Runtime

RISC-V out-of-order core for education and research purposes

An energy-efficient RISC-V floating-point compute cluster.

Open-source high-performance RISC-V processor

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.