munetomo-maruyama/mmRISC-2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.

Like VexRiscv, but, Harder, Better, Faster, Stronger

RISC-V CPU for OpenFPGAs, in Icestudio

A Linux-capable RISC-V multicore for and by the world

RSD: RISC-V Out-of-Order Superscalar Processor

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.