chipsalliance/sv-tests

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog language server

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

cocotb: Python-based chip (RTL) verification

Style guide enforcement for VHDL

VUnit is a unit testing framework for VHDL/SystemVerilog

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...