ARC-Lab-UF/sv-tutorial

Verilog HDL files

FPGA exercise for beginners

Digital Design with Chisel

Generator Bootcamp Material: Learn Chisel the Right Way

Learning FPGA, yosys, nextpnr, and RISC-V

A curated list of awesome resources for HDL design and verification

Veryl: A Modern Hardware Description Language

BaseJump STL: A Standard Template Library for SystemVerilog

EPFL logic synthesis benchmarks